1. Field of the Invention
This invention relates to multilayer thin film (MLTF) structure containing electronic packages such as multi-chip modules (MCM) and, more particularly, to a method for making engineering changes (EC's) in the electronic structure and/or repairing defective electrical connections in the MLTF structure using the conventional procedure of patterning the circuit design including orthogonal XY repair lines as if no changes or repairs are needed but without the need for deleting unwanted metallization such as via-pad connection straps for defective nets and XY repair line intersections and to the resulting MLTF structure and electronic component fabricated by the repair method.
2. Description of Related Art
Thin film electronic components offer an attractive packaging solution for high performance and light weight systems such as in computer, telecommunication, military and consumer applications. Though thin films offer high density interconnections, the manufacturing process typically produces some number of non-working interconnections due to process induced defects and a resulting low component product output yield. To assure the quality and reliability of the product, the defective interconnections need to be repaired to ensure their functionality, so as to assure a fault free electronic package.
Package interconnections consist of multiple layers of interconnections which are used to interconnect various parts of the system. After all the layers of the MLTF are fabricated, a final test is performed from the top surface of the package to separate defective interconnects from defect-free interconnects to guarantee the functionality of the interconnects and the package. Since a fully functioning package cannot support any defective interconnects, the package must either be thrown away, which is not feasible for thin film packages due to the high cost involved, or the defective interconnects can be repaired. The repair option accordingly represents an attractive solution for thin film packages.
In the past, repair schemes such as Direct Distribution Engineering Change (DDEC) as shown in U.S. Pat. No. 5,243,140 has been used whereby a series of `add` and `delete` repair operations have been used on a fixed metal layout on the top surface of the MLTF structure. In general, the repair scheme utilizes two correction pads arranged in an array, at least two direct distribution structures, a signal pad and conductor extending between at least two direct distribution structures.
In U.S. Pat. No. 4,254,445 a module for LSI chips includes an orthogonal array of sets of pads and fan-out metallization for a large number of chips. Running parallel to the sides of the chips and the fan-out area are several parallel prefabricated, thin film engineering change (EC) interconnection lines terminating in pads adjacent to the fan-out. The pads are arranged to permit discretionary connections of the fan outs to the EC pads with minimal crossovers by means of short fly wires.
U.S. Pat. No. 4,489,364 shows a chip carrying module including a number of EC change lines buried below the surface of the module. The EC lines are interrupted periodically to provide a set of vias extending up to the upper surface of the module between each set of chips where the vias are connected by dumbbell-shaped pads including narrow link which permits laser deletion. The fan-out pads can be connected to the pads by means of fly-wires.
U.S. Pat. Nos. 5,220,490 and 5,224,022 show custom interconnections done by personalizing (not repairing) the top metal wiring. The customizable circuit has a high density of orthogonally placed X and Y conductors capable of interconnecting closely spaced LSI circuits.
The above patents are incorporated herein by reference.
The typical thin film structure containing a number of interconnections using vias, pads and connecting conductor straps is shown in cross-section in FIG. 1 as number 10. The structure is typically mounted on a substrate (not shown) such as a ceramic material (MCM) containing wiring. The MLTF structure consists of a power plane or capture level 19, mesh 1 level 11, X wiring layer 12, Y wiring layer 13, ground plane mesh 2 layer 14 and a top surface metallurgy level (TSM) 15. The top surface metallurgy (TSM) level contains the (TSM) vias lo, via-pad strap connectors 18 and corresponding pads 17 for connecting chips to the thin film package. The top surface metallurgy level would also contain the repair wires such as orthogonal XY lines as shown in FIG. 2 as lines 30R, 30R', 31R and 31R' for correcting faulty interconnections or making EC's as discussed hereinbelow.
The terms net, via, defective net and defective via will be used interchangeably since they are related with the term net broadly defining a defective structure (nets consist of lines connected with vias between layers and a defect can occur on either a via or line segment--normally the line segment).
FIG. 2, which represents a partial top view of a typical MCM and of the TSM metallization level 15 of FIG. 1 shows one chip area bounded by the dotted lines 27, vias 16 and chip connection pads 17 (such as controlled collapse chip connection pads known as C4 pads) with the vias representing connections to the I/O in the MLTF structure and supporting substrate if any and the C4 pads represent the microsockets supporting the C4 balls connecting the chip to the thin film substrate. As can be seen from the figure, the C4 pads 17 are offset from the vias 16, which is preferable in high performance machines to ensure the elimination of any discontinuities which may arise due to the presence of the faulty interconnection still connected to the repaired wire. In the figure, the C4 pads are connected to the vias by conductor straps 18 that provide the connection for non-faulty interconnections. The strap 18 is conventionally created by a mask during the fabrication of the TSM and if the interconnection is faulty, a laser delete operation is necessary to disconnect the faulty interconnection from the C4 pad. Repair lines 30R, 30R', 31R and 31R' are orthogonal XY repair lines also conventionally created by a mask during the fabrication of the TSM and intersect at for example junction 34. A laser delete operation is also needed to separate the connected XY lines at their intersection or junction 34 with the needed X or Y repair line being continued past the junction by a subway as shown in FIG. 10. As will be more fully discussed hereinbelow, vias 16a and 16b were found to be part of defective interconnections and are not to be used. Corresponding pads 17a and 17b are shown connected to repair orthogonal lines 30R and 30R' by repair straps 18R and 18R', respectively. Using the method of the invention Y repair lines 30R and 30R' do not intersect with X repair line 31R at junction 34 and a metal delete step is therefore not required.
A repair method is disclosed in copending U.S. patent application Ser. No. 08/743,405 assigned to the assignee of the present invention. In this method interconnection defects are determined at the layer adjacent the top surface layer before the top surface layer is fabricated. The necessary repair lines are then known and the top surface metallurgy defined accordingly. There is still a need however to remove or delete unwanted metallurgy in the top surface metallurgy due primarily to the use of a mask which defines all the circuitry metallurgy regardless of the defects in the MLTF structure.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for repairing interconnections and/or making engineering changes in multilayer thin film containing electronic components such as MCMs without the need for deleting unwanted metallurgy such as via-pad connection straps for defective nets and intersecting XY repair lines which X and/or Y lines are needed to repair the defective nets but which connection straps and XY repair lines were formed for all nets regardless of defects.
Another object of the invention is to provide a method for repairing interconnections and/or making EC's in multilayer thin containing film electronic components employed on top of ceramic, laminate, dielectric or other substrates.
A further object of the invention is to provide a MLTF structure having repair lines and/or EC lines made using the method of the invention.
A still further object of the invention is to provide a multi-chip module containing a MLTF structure having repair lines and/or EC lines made using the method of the invention.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.